IBM Unveils Chip Architecture with Nearly Double Transistor Density, Claims Sub-1-Nanometer Breakthrough

IBM has introduced a new chip architecture that packs nearly 100 billion transistors onto a fingernail-sized chip, roughly doubling the transistor density of its previous generation. The company describes it as the world’s first sub-1-nanometer chip technology for AI data centers, promising major gains in compute performance and energy efficiency.

According to IBM Research director Jay Gambetta, this is not an incremental step but a meaningful leap toward more powerful computing without higher energy use. The 'sub-1-nanometer' label refers not to physical feature sizes but to a novel nanostack architecture that delivers the performance improvements expected from such tiny transistors.